FPGA Crossbar Switch Architecture for Partially Reconfigurable Systems

Partial reconfiguration offers several benefits for a system on chip. But in order to take advantage of this technique, easy access and low overhead must be provided. One key issue therefore is the on-chip communication architecture. Current reconfigurable systems use buses and fixed links, which are quite inflexible; recent proposals suggest using networks on chip instead. The problem of the latter approach is the high overhead which is required to control the dataflow. In this work, XBar is presented: a customized crossbar switch architecture for reconfigurable systems on chip, which provides flexibility without high control overhead. Channels are established in order to transfer data, and once the channel is set up, data can be delivered with a minimum of additional effort. Concurrent transmission is possible on all channels, so interruptions due to blocking cannot occur. Furthermore, new channel configurations can be established in a very short period of time, so frequent changes are possible. Since communication is buffered, the infrastructure may be used asynchronously and components of different clock domains can be connected. The scalability is worse than with a packet-switched network on chip and it is not possible to provide the same amount of flexibility. However, better overall results can be achieved particularly for throughput and latency for small systems. Furthermore, the design of partially reconfigurable modules is eased.